In a typical communications device, the peak voltage of a pure continuous wave (CW) signal is only √{square root over (2)} higher than its average (root mean square or RMS) voltage, exhibiting PAPR (peak to average power ratio, expressed in dB) of 3 dB. A signal composed of N independent equal amplitude CW's has a maximum peak value of N×√2 of the average value of one CW, and an RMS value of √N times the single CW average value. Thus, the maximum PAPR of that signal is 20×log 10(N×√(2/N))=10×log 10(N)+3 dB. PAPR increases logarithmically with the number of CW's.
The probability for encountering the high peak value is extremely small. For example, if N=30, the max PAPR could be ˜18 dB, but the probability that the peak of all independent CWs will align within ±5 degrees is (10/360)30=2×10−47.
When a RF signal is composed of multiple QAM carriers, the same equation can be used by using a single QAM carrier PAPR to replace the 3 dB of a CW PAPR. In order to quantify a “reasonable to occur” PAPR value, an evaluation of the rate at which the signal is sampled vs. the expected wait time is performed. For example, at a sample rate of 5 Gsps, 5×109 samples will be taken every second, making it very likely that a probability of 10−7 will occur every second, but very unlikely that a probability of 10−13 will occur every second.
The signal spectrum of several types of broadband communication schemes (such as wireless, cellular, WiFi, and CATV) is composed of deep modulation carriers (such as QAM and OFDM). Often, that spectrum is composed of multiple deep modulation carriers. As a result, the RF signal over these media suffers from high PAPR. High PAPR signals exhibit occasional very high instantaneous amplitude peaks which are much higher than the signal average value. Evaluating the nature of a typical CATV signal, a reasonably occurring peak (about once every second) can be ˜17 dB. While the probability of such very high peak levels is very low, the probability of lower peak values increases. For example, for the same signal, the probability goes up to 10−4 (average occurrence of once every ˜2 microseconds) for PAPR of about 12 dB.
It is customary to plot PAPR probability of a certain signal in a graph where the X-axis represents PAPRThreshold, and the Y-axis represent the probability of any PAPR higher than that PAPRThreshold. FIG. 1 is a graph that illustrates a PAPR plot for a typical CATV signal composed of 128×6 MHz channels of 256-QAM modulation in accordance with the known art.
The design of a communication device has to consider the expected PAPR values and their probability by allowing reasonably high instantaneous peaks to be processed with no or minimal distortion by the various components in the signal path. For example, a back off of ˜17 dB is typically used in a DAC (digital to analog converter) processing a broadband CATV signal. In other words, the average (RMS) voltage of the signal is set to be ˜17 dB below the DAC full scale (the maximum signal amplitude that can be handled by the DAC).
FIG. 2 is a time domain linear plot of a typical CATV(t) signal composed of 128×6 MHz channels of 256-QAM modulation in accordance with the known art. FIG. 2 depicts about 600,000 samples of the 768 MHz broad signal sampled at about 2.5 Gsps. Note that the signal has both positive and negative peaks.
FIG. 3 is an absolute linear value plot of the same signal as shown in FIG. 2, namely ABS(CATV(t)), in accordance with the known art. FIG. 4 is a plot of the same signal as shown in FIG. 2 in logarithmic scale, namely 20*log 10(ABS(CATV(t))), scaled with the RMS value at 0 dB, in accordance with the known art.
FIG. 5 is a chart depicting the 100 samples immediately near the highest PAPR recorded in the same signal as shown in FIG. 2 in accordance with the known art. As suggested by FIG. 5, it is typical to find several other peaks not far in value near a very high instantaneous peak. For example, in FIG. 5, two additional high peaks of just about 4 dB lower than the very high ˜14 dB peak are experienced in the signal very close to the very high ˜14 dB peak value.
Any practical DAC has a limited dynamic range, and thus it introduces noise and distortions to the signal it reconstructs from samples. Such noise and distortion may be described or characterized through various parameters such as ACLR (adjacent channel leakage ratio), SFDR (spurious free dynamic range), ENOB (effective number of bits), and the like. While the largest possible dynamic range is desirable to reduce noise and distortions, in practice the dynamic range is limited due to power consumption, cost, the available technology, and other constraints. Typically, the digital signal samples applied to the DAC are adjusted (by applying a digital gain) in their amplitude such that the average power value is sufficiently below the full scale of the DAC. That adjustment typically targets a certain probability for the signal PAPR peak to be higher than the DAC full scale. In addition, the signal is typically clamped before being applied to the DAC such that if a PAPR value higher than the DAC full scale does occur, a value equal to the DAC full scale is replacing the actual signal value. This replacement prevents a digital “wrap around” effect and ensures that the DAC creates an analog signal which is as close as possible to the original high PAPR peak value.
When a very high PAPR sample value occurs, which is above the full scale of the DAC, an error is introduced to the recreated analog signal at the output of the DAC. The clamping operation reduces the error amplitude (relative to a wraparound implementation). However, such an error, which typically is limited to a single DAC sample, is a real concern in a communication device. Being similar to a Dirac Delta or an impulse noise, the nature of such an error is that it manifests itself as a wide band noise that spreads over the in band operating bandwidth of the communicating device and can only be restricted in frequency by also affecting the out of band frequency range by analog blocking filters. The need to prevent these low probability peaks from creating noise events in band and out of band is the main motivation in setting the digital signal value such that the signal RMS level is set at a large back-off level relative to the DAC full scale.
However, given that the DAC dynamic range is limited, the higher the RMS signal back-off is from the DAC full scale, the closer is the RMS signal level to the noise level generated by the DAC. Thus, typically an optimization is implemented to compromise between the low probability of a large PAPR value exceeding the DAC full scale (and creating a short duration broadband noise event) and the overall “continuous noise floor” of the analog signal.
It is very desirable to increase the DAC dynamic range to enable handling very high large PAPR signals while keeping the DAC noise floor very low relative to the RMS signal value. However, there exist limitations in the available technology to achieve such a goal. Given a certain semiconductor technology, there is a steep trade off in energy efficiency (power consumption) to achieve even just a small increase in DAC dynamic range.
Modern high sample rate DAC implementations often use a current steering scheme. In such a scheme, a multitude of switched current elements are used, where each element is typically composed of a constant current source, a current steering switch, and optionally a current sink. Each current diversion switch is controlled by a logical signal, which is obtained from the sample to be processed by the DAC, to steer the current source to either the DAC output or to the current sink. Some implementations use the current diversion switch to divert the current between two separate outputs of the DAC (those being the positive and the negative outputs). This scheme is superior in accuracy relative to a scheme in which the current sources are directly turned on or off by the logical signal. This is so because current steering can be much faster than turning the current source on or off and because current steering is much less prone to a memory effect, where the current applied to the output load at one sample is affected by the current applied to the load during previous samples. Since the current sources of a current steering DAC are always on, its power consumption is relatively constant.
DACs used to process wide bandwidth signals are required to operate at high sample rate while possessing high dynamic range, and thus require a large number of effective bits. FIG. 6 is a simplified binary power DAC implementation used to process wide bandwidth signals in accordance with the prior art.
The simplified DAC implementation of FIG. 6 has a binary structure of current sources, where N current sources are arranged such that any successive current source has twice the current of its predecessor. Such a structure can handle a signal range of 2{circumflex over ( )}N digital values. The DAC performance, and its dynamic range, is limited by the accuracy of these current sources. For example, a 1% error in the current of the most significant current source is about 10 times larger than the current value of the 11th current source. Thus, small inaccuracies in the values of current sources, especially the larger value current sources, may limit the total accuracy and the dynamic range of the whole DAC. Fortunately, while the absolute current of each current source is hard to control in a typical semiconductor manufacturing process, the relative accuracy of such sources is much more controllable. Here, relative accuracy refers to the difference between the intended and actual ratios between these sources current. Nevertheless, achieving such high relative accuracy enabling large dynamic range very fast DACs with effective number of bits of 10 and above is still a great challenge.
FIG. 7 is an illustration of a DAC implementation having 2N equal value current sources to create a 2N signal range in accordance with the known art. The DAC of FIG. 7 requires a single “standard” current source and can result in a very repeatable and accurate DAC. However, the DAC implementation of FIG. 1 is often very expensive (in silicon real estate) due to the large number of current sources required to implement large N values as required for large dynamic range signals.
Due to practical reasons, the construction of high speed large dynamic range DACs often relies on a hybrid approach, where a small number of current source values (typically 2 or 3) is combined together to construct the DAC. Such a hybrid approach is shown in FIG. 8, which is an illustration of such a hybrid approach DAC implementation having a small number of current source values combined together in accordance with the known art.
If 2 current source values are used, M current sources of the smaller value I are in a first group and L (L=N−M) current sources of the larger value 2M×I are in the second group. For example, an 11 bit DAC can be constructed of 64 current sources of the value I, and 32 current sources of the value 64×I. The achievable relative accuracy of these sources is such that better accuracy and dynamic range is possible than in a binary power DAC composed of 11 current sources, while the total number of current sources in the hybrid DAC (96) is much smaller than in a “flat 11-bit DAC” requiring 2048 current sources. Similarly, a 3-group DAC can be constructed as well.
Note that the power consumption required by each current source is proportional to its set current value. Adding a 0.5×LSB (least significant bit) current source may be insignificant from a power consumption point of view, but it will also not benefit accuracy and dynamic range if the resulting signal is below the DAC noise floor. Adding a 2×MSB (most significant bit) current source may practically result in doubling the power consumption of the DAC. Such a 2×MSB current source will typically result in insignificant increase in the overall DAC accuracy and dynamic range since the relative accuracy of this 2×MSB current source (its accuracy relative to the lower value current sources) will likely become the limiting factor in the overall DAC accuracy).